1. Field of the Invention
The present invention generally relates to a chip package. More particularly, the present invention relates to a chip package with enhanced reliability and reduced production cost.
2. Description of Related Art
In recent years, chip package having a plurality of stacked chips is gradually developed. In most chip packages, the chips are stacked over and electrically connected to a carrier (e.g. a printed circuit board or a lead-frame) through bonding wires or bumps, such as gold bumps, copper bumps, polymer bump, or solder bumps. Generally, each of the chips stacked over the carrier is adhered with the other chips or the carrier by an adhesive (e.g. tapes or adhesion glue). Specifically, the tape with proper size and stickiness is attached on the chips or on the carrier when the tapes are used in the die-bonding process or chip-stacking process; and the adhesion glue is dispensed on the chips or on the carrier and is then cured when the adhesion glue is used in the die-bonding process or chip-stacking process. Since the tape must be cut into proper size in advance when using for performing the die-bonding process or chip-stacking process, the use of the tape is unfavorable to mass production. Additionally, the reliability of the chip package is affected because the thickness of the adhesion glue is difficult to control. Therefore, a solution is required to enhance the reliability and reduce the production cost of chip packages.